1. Field of the Invention
The present invention generally relates to a fabrication process of semiconductors. More particularly, the present invention relates to a fabrication method of a gate dielectric layer and.
2. Description of Related Art
Along with the rapid development in the Ultra-Large Scale Integration (ULSI) industry in recent years, circuit design is directed to a continuously reducing the size of devices. In order to increase the level of integration and the driving capacity, the line width of the gate is shorten and the thickness of gate dielectric layer is minimized correspondingly. In particular, as the semiconductor industry enters the era of deep submicron, the thickness of a gate dielectric layer is reduced from a couple hundred Å to about 40 Å. The fabrication of the gate dielectric layer in the ultra-Large Scale Integration (ULSI) technology is always an important matter. To produce an ultra thin gate dielectric layer with high quality while the process window is being reduced is an imminent problem to be resolved.
Applying thermal oxidation to fabricate a silicon oxide layer as a gate dielectric layer is well known in the art. However, pin holes are always present inside the structure of the silicon oxide layer leading to problems, such as the direct-tunnelling current . . . etc. Therefore, the aforementioned approach can not be used to form a thin gate dielectric layer. Other fabrication method known in the art includes performing a nitration treatment by introducing silicon nitride into a gate dielectric layer, which mainly contains silicon dioxide, to form a nitride oxide (NO) layer. The nitride oxide layer can reduce the leakage current and improve the reliability of the process. However, there are other problems existed with a stacked nitride oxide layer, formed with a silicon oxide layer and a nitride silicon layer, serving as a gate dielectric layer. For example, nitrogen atoms can easily diffuse through the interface between the silicon substrate and the silicon oxide layer during the nitration process to affect the efficiency and the stability of the devices. Besides, the interface between the silicon oxide layer and the silicon nitride layer can easily reduce the density of the trapped charges. Therefore, the efficiency and the stability of the devices are affected together with the reliability of the fabrication process.